Junyeol Ryu | Review

7/15/26 MemChannel (NSDI'26) CXL pooling, Sender-driven congestion control

7/15/26 RamRyder (OSDI'26) CXL pooling, bandwidth provisioning, SW

5/7/26 PhaseWeave (ISCA'26) Heterogeneous chiplet architecture

3/5/26 Packet Transactions (SIGCOMM'16) Programmable switch

2/24/26 TiNA (ASPLOS'26) Host network, Chiplet, Sub-NUMA Clustering, DMA

12/5/25 LithOS (SOSP'25) GPU scheduling, Multi-tenancy

11/25/25 Understanding the Host Network (SIGCOMM'24) Host network